Intel Sets a Base for Scalable Deep Learning
“Artificial intelligence is around us everywhere. It is becoming very commonplace,” said Diane Bryant, Intel’s executive vice president and general manager of the Data Center Group, keynoting the Intel Developer Forum, being held this week in San Francisco.
At the event, the company teased developers with promises of advanced applications in virtual reality, Internet of Things and ambient computing, all of which would require, of course, plenty of processing power, preferably, for the company, of the Intel sort. This year, Intel promoted artificial intelligence and machine learning (ML) as well.
Automated photo tagging, talk-to-text, fraud detection, precision medicine, autonomous automobiles all are benefiting from artificial intelligence, she said.
One of the main drivers of artificial intelligence is machine learning. About seven percent of all servers last year were deployed for machine learning. And this is growing. By 2020, there will be more servers running AI-driven analytics workloads than any other workload. “Machine learning and its subset techniques, deep learning, are key methods for expanding the field of artificial intelligence,” she said.
Machine learning, by its nature, is a distributed parallel high-performance workload, she noted. The math is not new, and not even difficult. It is simple linear algebra. But it does require scale.
“The more data you can compute, the more accurate the model, and the more compute you can throw at the model, the faster the model will train and converge,” Bryant said.
Currently, the Intel Xeon processor is the most widely deployed chip for ML. And the company is touting the next generation Xeon Phi chip, dubbed “Knight’s Landing” due in 2017, as being the true workhorse for machine learning. The chipset will include new instructions for variable precision floating point. “Xeon and Xeon Phi are inherently scalable architectures,” Bryant said (Although Nvidia recently charged that Intel had fluffed some of its Phi performance numbers).
The company has a lot of competition in this space, particularly from GPUs from the likes of Nvidia. Bryant had argued that, with ML, you want to do your development on the same processor that will handle the production work, so the training models would be accurate once they move into production. “Once you train an algorithm, you don’t want to recode and reoptimize it,” she said. Accelerators (like, say GPUs) will also add complexity to the programming, she argued.
To kickstart ML even further, Intel is optimizing a number of widely used ML frameworks so they will run more efficiently on Intel processors. There are Intel-optimized versions of Caffe and Theano, and soon the company will release optimized versions of TensorFlow, CNTK and Torch.
“We are investing to make sure all of those frameworks run outstanding on a single Xeon or Xeon Phi, but also make sure they run at scale,” Bryant said.
These frameworks are optimized by wiring them into a number of libraries that Intel has created to interact with its processors the most efficient way possible. These libraries include the Intel Math Kernel Library (MKL) and the Intel Data Analytics Acceleration Library (DAAL). Later this year, the company will also release a library for neural network training, called Deep Neural Network Math Kernel Library (MKL-DNN), as well as a software development kit for deep learning.
“Their IP, as well as their deep expertise in accelerating deep learning algorithms, will directly apply to our advancements in artificial intelligence,” she said. “They have solutions at the silicon level, the libraries and at the framework level.”
Intel is a sponsor of The New Stack.