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AI / API Management / Cloud Native Ecosystem / Hardware / Large Language Models / Operations

RISC-V Finds Its Foothold in a Rapidly Evolving Processor Ecosystem

But the open source processor architecture will need to find more support from the software dev community before it can rival x86 and ARM architectures in the data center: A wrap-up of RISC-V Summit in Barcelona.
Jul 28th, 2023 3:00am by
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Developers have grown up hearing ARM or x86 being the guts of PCs and servers, but an alternative architecture called RISC-V is emerging.

In the next few years, some companies will inevitably ship PCs and servers running on RISC-V processors. Those systems will likely run on Linux as Microsoft is not known to be developing a Windows OS for the architecture.

But there are big problems with the software ecosystem — the developer support is pitiful. RISC-V International, which is developing the chip architecture, talks more about hardware, with software a distant second in priorities.

Initial Support

Since its emergence close to a decade ago, RISC-V quickly gained the support of major chip makers, including Apple, which has put controllers in its Apple Silicon. About 10 billion chip cores based on RISC-V have shipped. Most recently, Meta announced an AI inferencing chip built on RISC-V architecture.

The chip architecture is often called a hardware equivalent of Linux. It is a free chip technology built on a contributor culture and the ethos of open source, in which a community works together to develop and improve the product.

RISC-V is a free-to-license architecture, which means anyone can fork a version of the architecture into their own chip.

Chips with RISC-V can be compiled like Lego blocks — companies that take the base architecture, and top it off with proprietary hardware blocks that may include accelerators for AI, graphics, or security.

“What was once an experiment, a prototype, is quickly moving into production,” said Calista Redmond, during a keynote at last month’s RISC-V Summit in Barcelona.

The structure of RISC-V makes it suitable for cloud native environments handling diverse applications and complex computing requirements.

The minimal base instructions are designed to quickly offload applications such as AI and analytics to accelerators like GPUs or specialized math processors, which excel at such tasks.

Chips from Intel and AMD are reaching their physical limits, and the flexibility of RISC-V provides a structure to move computing into the future.

For example, RISC-V provides a pathway for new hardware architectures such as sparse computing, which is being researched by the Intelligence Advanced Research Projects Activity, in which processing units are closer to the data in storage or memory.

The Barcelona Supercomputing Centre proposed the concept of merging CPU and memory in a RISC-V chip, which will reduce the memory bottleneck posed by machine-learning applications.


“What we want from it — it is actually to do memory-intensive operations close to memory, like memcpy,” said Umair Riaz, a researcher at BSC, referring to the C++ function to copy memory blocks. Riaz also referenced the spinlock function, and mentioned the CPU executing those in memory will be more efficient and faster.

“Executing functions locally you will eventually get performance and less [network] traffic because you are doing much more closer to memory,” Riaz said.

Writing applications for such complicated RISC-V chips may be a load for even the bravest programmers that want to code directly to the hardware. But Intel wants to provide the tooling needed for coders to start testing applications in simulated RISC-V environments.


Intel’s Codeplay software unit recently announced the OneAPI Construction Kit, which includes tools for developers to test code in a simulated RISC-V environment on x86 PCs.

The Construction Kit’s signature feature is support for SYCL — which allows coders to write and compile applications regardless of the hardware architecture — and Intel is taking the first steps to bring RISC-V support to the parallel-programming framework.

The kit includes support for Intel’s DPC++/C++ Compiler, which allows C++ code to be recompiled for use across multiple hardware architectures.

Developers can also test RISC-V code on Raspberry Pi-like developer boards or systems from companies such as Milk-V, and StarFive. Both companies offer high-performance 64-bit RISC-V systems with support for Linux.

Support for Linux tools on RISC-V are tepid. Only a handful of packages are fully supported, and that includes Ubuntu OS, Gnu Toolchain, OpenvSwitch, Apache Nuttx, and Spidermonkey for Mozilla.

Many packages for RISC-V will work reasonably well, but are still not fully supported. For example, the RISC-V developer community in China reported that more than 80% of the packages in open source Fedora are now supported on RISC-V,

Some key packages, such as Pytorch, GCC, TensorFlow, and OpenJDK will work, but are not yet fully supported. Support for open source applications like LibreOffice and Firefox are being built up. Google is accelerating its support of AOSP (Android Open Source Project) on RISC-V, which will be a big part of the next architecture specification.

RISC-V server chip makers Esperanto Technologies and Ventana Micro Systems have announced server chips for cloud computing, but have not talked much about software support or programming models. Esperanto has ported Meta’s Open Pre-Trained Transformer model to its RISC-V server.

RISC-V International, which is developing the architectural spec, is trying to solve that problem with the establishment of the RISC-V Software Ecosystem, also called RISE, to create the underlying software tools and middleware for RISC-V systems. The initial backers include companies such as Google, Intel, Nvidia, Qualcomm, Samsung, and Ventana.

Mark Himelstein, chief technology officer RISC-V International, at the summit talked about RISC-V taking a page from the cultural roots of Linux culture, with contributors contributing to the shared interests.

“That contributor culture means upstreaming on RISC-V and other communities where open source and open standards play a part,” Himelstein said, adding “that does not mean you are working on the pieces of the puzzle that are rapidly commoditizing.”

There is also no structure for hardware and software co-design that makes it easier for coders to use x86 and ARM systems. RISC-V first develops a hardware spec and Linux compatibility comes later. That is very different than Intel, which upstreams Linux drivers for a chip before it is released, which ensures the hardware is compatible with the latest build of the OS.

China, Tho

RISC-V’s software efforts also lack a force of nature like Linus Torvalds that can drive a project forward by sheer will. RISC-V also is not mainstream enough to attract an army of developers.

But it is a different scene with China, which is adopting RISC-V on a massive scale to create homegrown chips and reduce its reliance on Western technology. Developers in China are rolling up their sleeves and contributing coding to stand-up RISC-V compatible operating systems for Linux.

Their motivation is simple — an engineering focus is driving China’s RISC-V initiative, not politics, and there is plenty of motivation for developers to build OS support, especially with the latest Western chip technology out of sight due to export restrictions.

Chinese companies are developing some of the most sophisticated RISC-V chips, and the community is adding support for more packages daily. Many of the core contributors to Fedora, Debian, Gentoo and Arch Linux, GNU toolchain, and Clang are in China.

The RISC-V community in China is also leading a grassroots effort to bring support for ROCm — which is AMD’s parallel-programming framework — to RISC-V processors. AMD did not respond to requests for comment on whether it was involved in porting ROCm to RISC-V.

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